Advances in techniques for packaging semiconductor die are being driven by the market for smaller, lower cost electronic devices with increasing functionality. Chip scale packaging (CSP) encompasses a number of different packaging techniques where the size of the packaged die is only slightly larger than the size of the die itself.
In wafer level chip scale packaging (WLCSP), also referred to as wafer level packaging (WLP), the solder balls (or bumps) are formed directly on the semiconductor wafer, before the wafer is diced into individual die. This results in a very compact packaged die and enables wafer scale testing of packaged die, which may have cost and efficiency benefits. A variation of WLP is Embedded Wafer Level Ball Grid Array (eWLB) or Fan Out WLP (FOWLP, also referred to as Fan Out CSP). This packaging technology allows for a large number of connections by creating an artificial (or reconstituted) wafer that can then be post-processed using standard WLP techniques. The artificial wafer is formed by over-molding the diced semiconductor die which are held on a carrier and spaced by a distance which is typically larger than the spacing on the original silicon wafer. When the artificial wafer is diced, the die size is larger than the size of the semiconductor die, thus providing additional space for routing tracks and solder balls.
The embodiments described below are not limited to implementations which solve any or all of the disadvantages of known WLP methods.